Time interleaving is a technique that allows the use of multiple ADCs to process an analog input signal into a digital output signal at a faster rate than the operating sample rate of each individual data converter. Time interleaving comprises time multiplexing a parallel array of M identical ADCs, as shown in FIG. 1, to achieve a higher net sample rate 102 (fs with sampling period Ts=1/fs) even though each ADC in the array is actually sampling (and converting) at the lower rate of fs/M. So, for example, a 10-bit/400 MSPS ADC can be achieved by interleaving four 10-bit/100 MSPS (Mega Samples Per Second) ADCs.
FIG. 1 is an interleaved ADC 100 including a plurality of ADCs, including ADC1, ADC2, . . . ADCM. ADC 100 can include any number of ADCs. The inputs of the ADCs are coupled together for selectively receiving an input voltage VIN by analog switching front end circuitry 104. The outputs of the ADCs are correspondingly selectively coupled together by digital output multiplexer circuitry 106 for generating a composite output digital signal Dour representative of the input analog signal VIN. Interleaved ADC 100 has an effective sampling rate 102 of fs, whereas each individual ADC has a sampling rate of fs/M.
In FIG. 1 an analog input VIN(t) is sampled by the “M” ADCs and results in a combined digital output data series DOUT. ADC1 samples VIN(to) first and begins converting it into an n-bit digital representation. Ts seconds later, ADC2 samples VIN(to+Ts) and begins converting it into an n-bit digital representation. Then, Ts seconds later, ADC3 will sample VIN(t0+2 Ts) and so on. After ADCM has sampled VIN(to+(M−1)×Ts), the next sampling cycle starts over with ADC1 sampling VIN(to+M×Ts).
As the n-bit outputs of the ADCs become sequentially available in the same order as described for the sampling operation, these digital n-bit words are collected by the de-multiplexer shown on the right hand side of FIG. 1. Here the recombined data out sequence DOUT(to+L), DOUT(to+L+Ts), DOUT(to+L+2 Ts), . . . is generated. “L” stands for the fixed conversion time of each individual ADC and this recombined data sequence is an n-bit data series with sample rate fs. So, while the individual ADCs, often referred to as the “channels,” are n-bit ADCs sampling at fs/M, the interleaved ADC 100 is equivalent to a single n-bit ADC sampling at fs. The input analog signal VIN is separately processed by the ADCs in the interleaved ADC 100 and then reassembled at the output to form the high data rate representation DOUT of the input VIN.
FIG. 2 shows an example of a clocking scheme with individual clock signals for the case of M=4. The sample rate of each individual ADC in the interleaved ADC is fs/M, and the resulting sample rate 102 of the time interleaved ADC is fs.
While the sampling rate of the interleaved ADC can be increased relative to the sampling rate of an individual ADC in the interleaved ADC as shown, the digital output signal accuracy however can be degraded by relative differences in performance between the individual ADCs. For example, relative differences in offsets, gain, and skew (sampling time skew occurs when some of the channels sample earlier or later than at the designated time interval) between the individual ADCs can all degrade the accuracy of the overall reassembled digital output signal of the interleaved ADC.